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micro pmu with 1.2 a buck, two 300 ma ldos, supervisory, watchdog, and manual reset data sheet ADP5041 r ev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features input voltage range: 2.3 v to 5.5 v one 1.2 a buck regulator two 300 ma ldos 20-lead, 4 mm 4 mm lfcsp package overcurrent and thermal protection soft start undervoltage lockout open-drain processor reset with externally adjustable threshold monitoring guaranteed reset output valid to v avin = 1 v manual reset input watchdog refresh input buck key specifications output voltage range: 0.8 v to 3.8 v current mode topology for excellent transient response 3 mhz operating frequency peak efficiency up to 96% uses tiny multilayer inductors and capacitors mode pin selects forced pwm or auto pwm/psm mode 100% duty cycle low dropout mode ldos key specifications output voltage range: 0.8 v to 5.2 v low input supply voltage from 1.7 v to 5.5 v stable with 2.2 f ceramic output capacitors high psrr low output noise low dropout voltage ?40c to +125c junction temperature range functional block diagram sw en_bk 09652-001 fb2 r4 r4 r5 r3 fb3 r3 r7 c5 2.2f c6 2.2f vout2 avin vbias vbias vout1 fb1 l1 1h r1 r2 v in1 = 2.3v to 5.5v c1 4.7f supervisor p nrsto wdi vthr mr r filt = 30 ? v in2 = 1.7v to 5.5v vin1 on off on off on off en1 vin2 c2 1f c3 1f en2 en3 vin3 v in3 = 1.7v to 5.5v en_ldo2 ldo2 (analog) buck agnd v out1 at 1.2a c6 10f pgnd fpwm psm/pwm mode v out2 at 300ma v out3 at 300ma vout3 ldo1 (digital) en_ldo1 figure 1. general description the ADP5041 combines one high performance buck regulator and two low dropout regulators (ldo) in a small 20-lead lfcsp to meet demanding performance and board space requirements. the high switching frequency of the buck regulator enables use of tiny multilayer external components and minimizes board space. when the mode pin is set to logic high, the buck regulator operates in forced pwm mode. when the mode pin is set to logic low, the buck regulator operates in pwm mode when the load is around the nominal value. when the load current falls below a predefined threshold, the regulator operates in power save mode (psm), improving the light load efficiency. the low quiescent current, low dropout voltage, and wide input voltage range of the ADP5041 ldos extend the battery life of portable devices. the ADP5041 ldos maintain a power supply rejection greater than 60 db for frequencies as high as 10 khz while operating with a low headroom voltage. each regulator in the ADP5041 is activated by a high level on the respective enable pin. the output voltages of the regulators and the reset threshold are programmed through external resistor dividers to address a variety of applications. the ADP5041 contains supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. they also provide power-on reset signals. an on-chip watchdog timer can reset the microprocessor if it fails to strobe within a preset timeout period.
ADP5041 data sh eet rev. 0 | page 2 of 40 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 general specifications ................................................................. 3 supervisory specifications .......................................................... 3 buck specifications ....................................................................... 4 ldo1, ldo2 specifications ....................................................... 5 input and output capacitor, recommended specifications .. 6 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 26 power management unit ........................................................... 26 buck section ................................................................................ 27 ldo section ............................................................................... 28 supervisory section ................................................................... 28 applications information .............................................................. 31 buck external component selectio n ....................................... 31 ldo external component selection ...................................... 32 output capacitor ........................................................................ 32 sup ervisory section ................................................................... 33 power dissipation/thermal considerations ............................. 34 application diagram ................................................................. 36 pcb layout guidelines .................................................................. 37 suggested layout ........................................................................ 37 bill of materials ........................................................................... 38 factory programmable options ................................................... 39 outline dimensions ....................................................................... 40 ordering guide .......................................................................... 40 revision history 12/ 11 revision 0: initial version
data sheet ADP5041 rev. 0 | page 3 of 40 specifications general specificatio n s avin, v in1 = 2.3 v to 5. 5 v ; avin, v in1 vin2, vin3; vin2, vin3 = 1.7 v to 5.5 v, t j = ? 40 c to +125 c for minim um/maximum specifications, and t a = 25 c for t ypical specifications , unless otherwise noted. table 1. parameter symbol test conditions/comments min typ max unit avin undervoltage lockout uvlo avin input voltage rising uvlo avinrise option 0 2.275 v option 1 3.9 v input voltage falling uvlo avinfall option 0 1.95 v option 1 3.1 v shutdown current i gnd - sd enx = gnd 0.1 2 a thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 20 c start - up time 1 b uck t start1 250 s ldo1, ldo2 t start 2 v out2 , v out3 = 3.3 v 85 s enx, wdi, mode, mr inputs input logic high v ih 2.5 v avin 5.5 v 1.2 v input logic low v il 2.5 v avin 5.5 v 0.4 v input leakage current v i- lea kage enx = avin or gnd 0.05 1 a open - drain output nrsto output voltage v ol 1v a vin 1.0 v, i sink = 50 a 0.3 v v ol 1v2 a vin 1.2 v, i sink = 100 a 0.3 v v ol 2v7 a vin 2.7 v, i sink = 1.2 ma 0.3 v v ol 4v5 a vin 4.5 v, i sink = 3.2 ma 0.4 v open - drain reset output leakage current avin = 5.5 v 1 a 1 s tart - up time is defined as the time from the moment en1 = en2 = en3 transfers from 0 v to vavin to the moment vout1, vout2, and vo ut3 are reaching 90% of their nominal levels. start - up times are shorter for individual channels if another channel is already enabled. see the typical performance characteristics section for more information. supervisory specific ation s avin, v in1 = 2.3 v to 5.5 v; t j = ? 40 c to +125 c for minimum/maximum specifications, and t a = 25 c for typical specifications , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments supply supply current (supervisory circuit only) 45 55 a avin = vin1 = en1 = en2 = en3 = 5.5 v 43 52 a avin = vin1 = en1 = en2 = en3 = 3.6 v threshold voltage 0.495 0.500 0.505 v reset timeout period option 0 24 30 36 ms option 1 160 200 240 ms v cc to reset delay (t rd ) 80 s vin falling at 1 mv/s
ADP5041 data sheet rev. 0 | page 4 of 40 parameter min typ max unit test conditions/comments watchdog input watchdog timeout period option 0 81.6 102 122.4 ms option 1 1.28 1.6 1.92 sec wdi pulse width 80 n s v il = 0.4 v, v ih = 1.2 v wdi input threshold 0.4 1.2 v wdi input current (source) 8 15 20 a v wdi = v cc , time average wdi input current (sink) ?30 ?25 ? 15 a v wdi = 0 v , time average manual reset input mr input pulse width 1 s mr g litch rejection 220 n s mr pull - up resistance 25 52 90 k? mr to reset delay 280 n s v cc = 5 v b uck specifications a v in, vin 1 = 2.3 v to 5.5 v; v out 1 = 1.8 v ; l = 1 h; c in = 10 f ; c out = 10 f; t j = ?40c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. 1 table 3. parameter symbol test conditions/comments min typ max unit input characteristics input voltage range v in1 2.3 5.5 v output characteristics output voltage accuracy v out1 pwm mode, i load = 0 ma to 1200 ma ?3 +3 % line regulation (v out1 /v out1 )/v in1 pwm mode ? 0. 05 %/v load regulation ( v out1 /v out1 )/ i out1 i load = 0 ma to 1200 ma, pwm mode ? 0. 1 %/a voltage feedback v fb1 0.485 0.5 0 . 515 v pwm to power save mode current threshold i psm_l 100 ma input current characteristics mode = ground dc operating current i noload i load = 0 ma, device not switching , all other channels disabled 21 35 a shutdown current i shtd en1 = 0 v, t a = t j = ?40c to +125c 0.2 1.0 a sw characteristics sw on resistance r pfet pfet , avin = vin1 = 3.6 v 180 240 m? pfet, avin = vin1 = 5 v 140 190 m? r nfet nfet , avin = vin1 = 3.6 v 170 235 m? nfet, avin = vin1 = 5 v 150 210 m? current limit i limit pfet switch peak current limit 1600 1950 2300 ma active pull - down en1 = 0 v 85 ? oscillator frequency f osc 2.5 3.0 3.5 mhz 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc).
data sheet ADP5041 rev. 0 | page 5 of 40 ldo 1, ldo2 specifications v in2, v in3 = (v out 2 ,v out 3 + 0.5 v) or 1.7 v ( whichever is greater ) to 5.5 v ; avin, vin1 vin2, vin3; c in = 1 f , c out = 2.2 f; t j = ?40c to +125c for minimum/maximum specifications and t a = 25c for typical specifications, unless o therwise noted. 1 table 4. parameter symbol conditions min typ max unit input voltage range v in 2 , v in 3 t j = ?40c to +125c 1.7 5.5 v operating supply curren t bias current per ldo 2 i vin2bias / i vin3bias i out3 = i out4 = 0 a 10 30 a i out2 = i out3 = 10 ma 60 100 a i out2 = i out3 = 300 ma 165 245 a total system input current i in includes all current into avin, vin1, vin2 , and vin3 ldo1 or ldo2 only i out2 = i out3 = 0 a , all other channels disabled 53 a ld o1 and ldo2 only i out2 = i out3 = 0 a, buck disabled 74 a output voltage accuracy v out2 , v out3 100 a < i out2 < 300 ma, 100 a < i out3 < 300 ma vin2 = (vout2 + 0.5 v) to 5.5 v vin3 = (vout3 + 0.5 v) to 5.5 v ?3 +3 % reference voltage v fb2 , v fb 3 0.485 0.500 0.515 v regulation line regulation (v out2 /v out2 )/v in2 (v out3 /v out3 )/v in3 vin2 = (vout2 + 0.5 v) to 5.5 v vin3 = (vout3 + 0.5 v) to 5.5 v ?0.03 +0.03 % / v i out2 = i out3 = 1 ma load regu lation 3 ( v out2 /v out2 )/ i out2 ( v out3 /v out3 )/ i out3 i out2 = i out3 = 1 ma to 300 ma 0.002 0.0075 %/ma dropout voltage 4 v dropout v out2 = v out3 = 5.0 v, i out2 = i out3 = 300 ma 72 mv v out2 = v out3 = 3.3 v, i out2 = i out3 = 300 ma 86 140 mv v o ut2 = v out3 = 2.5 v, i out2 = i out3 = 300 ma 107 mv v out2 = v out3 = 1.8 v, i out2 = i out3 = 300 ma 180 mv active pull - down r pdldo en2/en3 = 0 v 600 ? current - limit threshold 5 i limit t j = ?40c to +125c 335 470 ma output noise out ldo2noise 10 hz to 100 khz, v in3 = 5 v, v out3 = 3.3 v 123 v rms 10 hz to 100 khz, v in3 = 5 v, v out3 = 2.8 v 110 v rms 10 hz to 100 khz, v in3 = 5 v, v out3 = 1.5 v 59 v rms out ldo1noise 10 hz to 100 khz, v in2 = 5 v, v out2 = 3.3 v 140 v rms 10 hz to 1 00 khz, v in2 = 5 v, v out2 = 2.8 v 129 v rms 10 hz to 100 khz, v in2 = 5 v, v out2 = 1.5 v 66 v rms power supply rejection ratio psrr 1 khz, v in2 , v in3 = 3.3 v, v out2 , v out3 = 2.8 v, i out = 100 ma 66 db 100 khz, v in2 , v in3 = 3.3 v, v out2 , v ou t3 = 2.8 v, i out = 100 ma 57 db 1 mhz, v in2 , v in3 = 3.3 v, v out2 , v out3 = 2.8 v, i out = 100 ma 60 db 1 all limits at temperatu re extremes are guaranteed via correlation using standard statistical quality control (sqc). 2 thi s is the input current into vin2 and vin3 that is not delivered to the output load. 3 based on an end - point calculation using 1 ma and 30 0 ma loads. 4 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output voltage. this applies only to output voltages above 1.7 v. 5 current - limit threshold is defined as the current at which the output voltage d rops to 90% of the specified typical value. for example, the current limit for a 3 . 0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 v, or 2.7 v.
ADP5041 data sheet rev. 0 | page 6 of 40 input and output cap acitor, recommended specifications table 5. parameter symbol test conditions /comments min typ max unit in put capacitance (b uck ) 1 c min 1 t j = ?40c to +125c 4.7 40 f output capacitance (buck) 2 c min 2 t j = ?40c to +125c 7 40 f input and output capacitance 3 (ldo1, ldo2) c min 34 t j = ?40c to +125c 0.70 f capacitor esr r esr t j = ?40c to +125c 0.001 1 ? 1 the minimum in put capa citance should be greater than 4 . 7 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capacitors are recommended, wher eas y5v and z5u capacitors are not recommended for use with the buck. 2 the minimum output capa citance should be greater than 7 f over the full range of operating conditions. the full range of operating conditions in the application must be considered dur ing device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capacitors are recommended, whereas y5v and z5u capacitors are not recommended for use with the buck. 3 the minimum input and output capacitance should be gr eater than 0. 7 0 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capacitors ar e recommended, whereas y5v and z5u capacitors are not recommended for use with ldos.
data sheet ADP5041 rev. 0 | page 7 of 40 absolute maximum rat ings table 6. parameter rating avin to a gnd ? 0.3 v to + 6 v vin1 to avin ?0.3 v to + 0.3 v pgnd to agdn ?0.3 v to + 0.3 v vin2 , vin3, voutx, enx, mode, mr , wdi, nrsto , fbx, vthr, sw to a gnd ?0.3 v to (avin + 0.3 v ) sw to pgnd ?0.3 v to (vin1 + 0.3 v) storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j - std -020 esd human body model 3000 v esd charged device model 1500 v esd machine model 200 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 7 . thermal resistance package type ja jc unit 20- lead , 0.5 mm p itch l fcsp 38 4.2 c/w esd caution
ADP5041 data sheet rev. 0 | page 8 of 40 pin configuration an d function descripti ons 09652-002 14 1 3 12 1 3 4 vout2 15 fb2 vin2 fb1 1 1 vout1 fb3 vin3 2 vout3 en3 5 nrs t o 7 vin1 6 a vin 8 sw 9 pgnd 10 en1 19 wdi 20 mr 18 vthr 17 mode 16 en2 ADP5041 t op view (not to scale) notes 1. exposed pad must be connected to system ground plane. figure 2 . pin configuration view from t op of the die table 8 . pin function descriptions pin no. mnemonic description 1 fb3 ldo2 feedback input . 2 vout3 ldo2 output voltage . 3 vin3 ldo2 input supply (1.7 v to 5.5 v) . 4 en3 enable ldo2. en3 = h igh : t urn o n ldo2; en3 = low : t urn off ldo2. 5 nrsto open - drain r eset o utput, a ctive l ow . 6 avin housekeeping and supervisory input supply (2.3 v to 5.5 v) . 7 v in1 b uck input supply (2.3 v to 5.5 v) . 8 sw b uck s witching n ode . 9 pgnd dedicated power ground for b uck r egulator . 10 en1 enable buck. en1 = h igh : t urn o n b uck ; en1 = low : t urn off buck . 11 vout1 b uck output sensing node . 12 fb1 b uck feedback input . 13 vin2 ldo1 input supply (1.7 v to 5.5 v) . 14 vout2 ldo1 output voltage . 15 fb2 ldo1 feedback input . 16 en2 enable ldo1. en2 = h igh : t urn o n ldo1; en2 = low : t urn o ff ldo1. 17 mode buck mode. m ode = h i gh ; buck regulator operates in fixed pwm mode; m o de = l ow ; b uck regulator operates in power sav ing mode (psm) at light load and in constant pwm at higher load. 18 vthr reset t hreshold programming . 19 wdi watchdog refresh i nput from p rocessor. if wdi is in h i gh -z, w atchdog is disabled . 20 mr manual reset input, a ctive l ow. 0 epad exposed pad ( analog groun d). the e xposed pad must be connected to the system g round p lane .
data sheet ADP5041 rev. 0 | page 9 of 40 typical performance characteristics vin1 = vin2 = vin3 = avi n = 5.0 v, t a = 25c, unless otherwise noted. 09652-003 ch4 2.0v/div 1m? b w 500m ch2 2.0v/div 1m? b w 20.0m ch3 2.0v/div 1m? b w 500m a ch2 1.88v 200s/div 1.0ms/s 1.0s/pt 4 2 3 v out1 v out2 v out3 figur e 3 . 3 - channel start - up waveforms 09652-004 ch1 ch2 ch3 ch4 a ch1 1.08v 200s/div 5.0ms/s 200ns/pt 1 2 3 4 v out3 v out2 v out1 i in 2.0v/div 1m? b w 20.0m 2.0v/div 1m? b w 20.0m 300ma/div 1m? b w 20.0m 2.0v/div 1m? b w 20.0m figure 4 . total in rush current, all channels started simultaneously 1.0 0 2.4 2.9 3.4 3.9 4.4 4.9 5.4 i in (ma) v in (v) 09652-005 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 figure 5 . system quiescent current (sum of all the input currents) vs. input voltage v out1 = 1.8 v, v out2 = v out3 = 3.3 v , (uvlo = 3.3 v) 09652-006 ch1 ch2 ch3 ch4 a ch1 2.32v 50s/div 2.0ms/s 500ns/pt 1 2 3 4 sw v out1 en i in 4.0v/div 1m? b w 20.0m 3.0v/div 1m? b w 500m 200ma/div 1m? b w 20.0m 5.0v/div 1m? b w 500m figure 6 . buc k startup, v out 1 = 3.3 v, i out2 = 20 ma 09652-007 ch1 ch2 ch3 ch4 a ch1 1.12v 50s/div 2.0ms/s 500ns/pt 1 2 3 4 sw v out1 en i in 8.0v/div 1m? b w 20.0m 2.0v/div 1m? b w 500.0m 200ma/div 1m? b w 20.0m 5.0v/div 1m? b w 500.0m figure 7 . buck startup, v out1 = 1.8 v, i out = 20 ma 09652-008 ch1 ch2 ch3 ch4 a ch1 640mv 50s/div 2.0ms/s 500ns/pt sw v out1 en i in 8.0v/div 1m? b w 20.0m 2.0v/div 1m? b w 500.0m 200ma/div 1m? b w 20.0m 5.0v/div 1m? b w 500.0m 1 2 3 4 figure 8 . buck startup, v out1 = 1.2 v, i out = 20 ma
ADP5041 data sheet rev. 0 | page 10 of 40 3.90 3.70 0.01 0.1 1 output voltage (v) output current (a) 3.72 3.74 3.76 3.78 3.80 3.82 3.84 3.86 3.88 ?40c +25c +85c 09652-009 figure 9 . buck load regulation across temperature , v out1 = 3 .8 v, auto mode 3.39 3.37 3.35 3.33 3.31 3.29 3.25 3.27 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09652-010 figure 10 . buck load regula tion across temperature , v out1 = 3.3 v , auto mode 1.820 1.815 1.810 1.800 1.805 1.795 1.790 1.780 1.785 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09652-0 1 1 figure 11 . buck load regulation across temperature, v out1 = 1.8 v, auto mode 1.24 1.23 1.22 1.21 1.20 1.19 1.18 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09652-012 figure 12 . buc k load regulation across temperature, v out1 = 1.2 v, auto mode 3.90 3.88 3.86 3.70 3.72 3.74 3.76 3.78 3.80 3.82 3.84 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09652-013 figure 13 . buck load regulation across temperature, v out1 = 3.8 v, pwm mode 3.32 3.31 3.30 3.25 3.26 3.27 3.28 3.29 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09652-014 figure 14 . buck load regulation across temperature, v out1 = 3.3 v, pwm mode
data sheet ADP5041 rev. 0 | page 11 of 40 1.820 1.815 1.810 1.800 1.805 1.795 1.790 1.780 1.785 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09652-015 figure 15 . buck load regulation across tempe rature, v out1 = 1.8 v, pwm mode 1.205 1.200 1.195 1.185 1.190 1.180 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09652-016 figure 16 . buck load regulation across temperature, v out1 = 1.2 v, pwm mode 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 5.5v v in = 4.5v 09652-017 figure 17 . buck efficiency vs. load current, across input voltage , v out 1 = 3 .8 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 5.5v v in = 4.5v 09652-018 figure 18 . buck efficiency vs. load current, across input voltage, v out1 = 3.8 v, pwm mode 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 5.5v v in = 4.5v v in = 3.6v 09652-019 figure 19 . buck efficiency vs. load current, across input voltage, v out1 = 3.3 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 5.5 v in = 3.6 v in = 4.5 09652-020 figur e 20 . buck efficiency vs. load current, across input voltage, v out1 = 3.3 v, pwm mode
ADP5041 data sheet rev. 0 | page 12 of 40 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v 09652-021 figure 21 . buck efficiency vs. load current, across input voltage, v out1 = 1.8 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 09652-022 v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v figure 22 . buck efficiency vs. load current, across input voltage, v out1 = 1.8 v, pwm mode 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 09652-023 v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v figure 23 . buck efficiency vs. load current, across input voltage, v out1 = 1.2 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 09652-024 v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v figure 24 . buck efficiency vs. load current, across input voltage, v out1 = 1.2 v, pwm mode 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09652-025 figure 25 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 3.3 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09652-026 figure 26 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 3.3 v, pwm mode
data sheet ADP5041 rev. 0 | page 13 of 40 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09652-027 figure 27 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 1.8 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09652-028 figure 28 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 1.8 v, pwm mode 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09652-029 figure 29 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 1.2 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09652-030 figure 30 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 1.2 v, pwm mode 2.5 2.0 0.5 1.0 1.5 0 3.4 3.9 4.4 4.9 5.4 output current (a) v in (v) v out = 3.3v 09652-031 figure 31 . buck dc current capability vs. input voltage 2.0 1.8 0.2 0.4 0.6 0.8 1.6 1.4 1.2 1.0 0 2.4 3.9 3.4 2.9 4.4 4.9 5.4 output current (a) v in (v) v out = 1.8v 09652-032 figure 32 . buck dc current capability vs. input voltage
ADP5041 data sheet rev. 0 | page 14 of 40 2.0 1.8 0.2 0.4 0.6 0.8 1.6 1.4 1.2 1.0 0 2.4 3.9 3.4 2.9 4.4 4.9 5.4 output current (a) v in (v) v out = 1.2v 09652-033 figure 33 . buck dc current capability vs. input voltage 2.80 2.82 2.84 2.86 2.88 2.90 2.92 2.94 0 1.2 1.0 0.2 0.4 0.6 0.8 frequency (mhz) output current (a) ?40c +25c +85c 09652-034 figure 34 . buck switching frequency vs. output current, across temperature, v out1 = 1.8 v, pwm mode ch2 ch3 ch4 a ch1 640mv 5s/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 40.0mv/div 20.0m 2 3 4 09652-035 figure 35 . typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, auto mode ch2 ch3 ch4 a ch1 640mv 5s/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 40.0mv/div 20.0m 2 3 4 09652-036 figure 36 . typical waveforms, v out1 = 1.8 v, i out1 = 30 ma, auto mode ch2 ch3 ch4 a ch3 1.14v 5s/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 40.0mv/div 20.0m 2 3 4 09652-037 figure 37 . typical waveforms, v out1 = 1.2 v, i out1 = 30 ma, auto mode ch2 ch3 ch4 a ch1 640mv 200ns/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 10.0mv/div 20.0m 2 3 4 09652-038 figure 38 . typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, pwm mode
data sheet ADP5041 rev. 0 | page 15 of 40 ch2 ch3 ch4 a ch1 640mv 200ns/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 20.0mv/div 20.0m 2 3 4 09652-039 figure 39 . typical waveforms, v out1 = 1.8 v, i out1 = 30 ma, pwm mode ch2 ch3 ch4 a ch3 1.14v 200ns/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 40.0mv/div 20.0m 2 3 4 09652-040 figure 40 . typical waveforms, v out1 = 1.2 v, i out1 = 30 ma, pwm mode ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 50.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 400m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09652-041 figure 41 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 3.3 v, i out 1 = 5 ma , auto mode ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 30.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 400m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09652-042 figure 42 . buck response to lin e transient, input voltage from 4.5 v to 5.0 v, v out1 = 1.8 v, i out 1 = 5 ma, auto mode ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 50.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 400m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09652-043 figure 43 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 1.2 v, i out 1 = 5 ma, auto mode ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 50.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 400m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09652-044 figure 44 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 3.3 v, pwm mode
ADP5041 data sheet rev. 0 | page 16 of 40 ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 20.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 400m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09652-045 figure 4 5 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 1.8 v, pwm mode ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 50.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 20.0m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09652-046 figure 46 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 1.2 v, pwm mode ch1 ch2 ch3 a ch3 150m a v out sw 4.0v/div 100mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 2 1 3 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09652-047 figure 47 . buck r esponse to load transient, i out1 = 20 ma to 200 ma, v out1 = 3.3 v, auto mode ch1 ch2 ch3 a ch3 150m a v out sw 4.0v/div 100mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 2 1 3 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09652-048 figure 48 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 3.3 v, auto mode ch1 ch2 ch3 a ch3 150m a v out sw 4.0v/div 100mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 2 1 3 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09652-049 figure 49 . buck response to load transient, i out1 = 20 ma to 200 ma, v out1 = 1.8 v, auto mo de ch1 ch2 ch3 a ch3 150m a 2 3 v out sw 4.0v/div 100mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 1 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09652-050 figure 50 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 1.8 v, auto mode
data sheet ADP5041 rev. 0 | page 17 of 40 ch1 ch2 ch3 a ch3 94.0m a 2 3 v out sw 4.0v/div 50.0mv/div 1m? b w 120m 1m? b w 20.0m 100ma/div 1 b w 20.0m 200s/div 500ks/s 2.0s/pt i out 09652-051 figure 51 . buck response to load transient, i out1 = 20 ma to 200 ma, v out1 = 1.2 v, auto mode ch1 ch2 ch3 a ch3 92.0m a 2 3 v out sw 4.0v/div 50.0mv/div 1m? b w 120m b w 20.0m 200ma/div 1 b w 20.0m 200s/div 500ks/s 2.0s/pt i out 09652-052 f igure 52 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 1.2 v, auto mode ch1 ch2 ch3 a ch3 150m a 2 3 v out sw 4.0v/div 50.0mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 1 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09652-053 figure 53 . buck response to load transient, i out1 = 20 ma to 200 ma, v out1 = 3.3 v, pwm mode ch1 ch2 ch3 a ch3 150m a 2 3 v out sw 4.0v/div 50.0mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 1 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09652-054 figure 54 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 3.3 v, pwm mode ch1 ch2 ch3 a ch3 150m a 2 3 v out sw 4.0v/div 50.0mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 1 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09652-055 figure 55 . buck response to load transient, i out1 = 20 ma to 200 ma, v out1 = 1.8 v, pwm mode ch1 ch2 ch3 a ch3 150m a 2 3 v out sw 4.0v/div 100mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 1 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09652-056 figure 56 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 1.8 v, pwm mode
ADP5041 data sheet rev. 0 | page 18 of 40 sw ch1 ch2 ch3 a ch3 94.0m a 2 3 v out 4.0v/div 50.0mv/div 1m? b w 120.0m b w 20.0m 100ma/div 1 b w 20.0m 200s/div 500ks/s 2.0ns/pt i out 09652-057 figure 57 . buck response to load transient, i out1 = 20 ma to 200 ma, v out1 = 1.2 v, pwm mode ch1 ch2 ch3 a ch3 92.0m a 2 3 v out 4.0v/div 50.0mv/div 1m? b w 20.0m 20.0m 200ma/div 1 20.0m 200s/div 500ks/s 2.0ns/pt sw i out 09652-058 figure 58 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 1.2 v, pwm mode ch1 ch2 ch3 a ch1 1.72v 2 3 v out 2.0v/div 2.0v/div b w 20.0m 1m? b w 20.0m 200ma/div 1 1m? b w 20.0m 50.0s/div 200ms/s 5.0ns/pt i in en 09652-059 figure 59 . ldo1, ldo2 startup, v out = 4.7 v, i out = 5 ma ch1 ch2 ch3 a ch1 1.72v v out 2.0v/div 2.0v/div b w 20.0m 1m? b w 20.0m 200ma/div 1m? b w 20.0m 50.0s/div 200ms/s 5.0ns/pt i in en 09652-060 figure 60 . ldo1, ldo2 startup, v out = 3.3 v, i out = 5 ma ch1 ch2 ch3 a ch1 760mv 2 3 v out 2.0v/div 1.0v/div b w 20.0m 1m? b w 20.0m 200ma/div 1 1m? b w 20.0m 50.0s/div 200ms/s 5.0ns/pt i in en 09652-061 figure 61 . ldo1, ldo2 startup, v out = 1.8 v, i out = 5 ma ch1 ch2 ch3 a ch1 1.72v 2 3 v out 2.0v/div 1.0v/div b w 20.0m 1m? b w 20.0m 200ma/div 1 1m? b w 20.0m 50.0s/div 200ms/s 5.0ns/pt i in en 09652-062 figure 62 . ldo1, ldo2 startup, v out = 1.2 v, i out = 5 ma
data sheet ADP5041 rev. 0 | page 19 of 40 4.758 4.708 4.658 4.608 0.001 0.01 0.1 output voltage (v) output current (a) 5.5v 5.0v 09652-063 figure 63 . ldo1, ldo2 load regulation across inpu t voltage, v out = 4.7 v 3.40 3.20 0.001 0.01 0.1 output voltage (v) output current (a) 5.5v 3.6v 4.5v 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 09652-064 figure 64 . ldo1, ldo2 load regulation across input voltage, v out = 3.3 v 1.800 1.770 0.001 0.01 0.1 output voltage (v) output current (a) 1.775 1.780 1.785 1.790 1.795 3.6v 4.5v 5.5v 2.8v 09652-065 figure 65 . ldo1, ldo2 load regulation across input voltage, v out = 1.8 v 1.220 1.180 0.001 0.01 0.1 output voltage (v) output current (a) 3.6v 4.5v 5.5v 2.8v 1.185 1.190 1.195 1.200 1.205 1.210 1.215 09652-066 figure 66 . ldo1, ldo2 load regulation across input voltage, v out = 1.2 v 3.40 3.20 0.001 0.01 0.1 output voltage (v) output current (a) 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 ?40c +25c +85c 09652-067 figure 67 . ldo1, ldo2 load regulation across temperature, v in = 3.6 v, v out = 3.3 v 1.800 1.770 0.001 0.01 0.1 output voltage (v) output current (a) ?40c +25c +85c 1.775 1.780 1.785 1.790 1.795 09652-068 figure 68 . ldo1, ldo2 load regulation ac ross temperature, v in = 3.6 v, v out = 1.8 v
ADP5041 data sheet rev. 0 | page 20 of 40 1.220 1.180 0.001 0.01 0.1 output voltage (v) output current (a) 1.185 1.190 1.195 1.200 1.205 1.210 1.215 ?40c +25c +85c 09652-069 figure 69 . ldo1, ldo2 load regulation across temperature, v in = 3.6 v, v out = 1.2 v 4.75 4.73 4.65 4.67 4.69 4.71 5.0 5.1 5.5 5.4 5.3 5.2 output voltage (v) input voltage (v) 100a 1ma 10ma 100ma 200ma 09652-070 figure 70 . ldo1, ldo2 line regulation across input voltage, v out = 4. 7 v 3.310 3.280 3.6 3.9 4.2 4.5 5.1 4.8 5.4 output voltage (v) input voltage (v) 3.285 3.290 3.295 3.300 3.305 100a 1ma 10ma 100ma 200ma 09652-071 figure 71 . ldo1, ldo2 line regulation across input voltage, v out = 3.3 v 1.820 1.790 2.5 3.0 3.5 4.0 5.0 4.5 5.5 output voltage (v) input voltage (v) 100a 1ma 10ma 100ma 200ma 1.795 1.800 1.805 1.810 1.815 09652-072 figure 72 . ldo1, ldo2 line regulation across input voltage, v out = 1.8 v 1.201 1.192 2.5 5.5 output voltage (v) input voltage (v) 1.193 1.194 1.195 1.196 1.197 1.198 1.199 1.200 3.0 3.5 4.0 4.5 5.0 100 a 1m a 10m a 100m a 200m a 09652-073 figure 73 . ldo1, ld o2 line regulation across input voltage, v out = 1.2 v 200 0 0 0.05 0.10 0.15 0.20 0.25 0.30 ground current (a) output current (a) 20 40 60 80 100 120 140 160 180 09652-074 figure 74 . ldo1, ldo2 ground current vs. output current , v out = 3.3 v
data sheet ADP5041 rev. 0 | page 21 of 40 200 0 3.8 4.3 4.8 5.3 ground current (a) input voltage (v) 20 40 60 80 100 120 140 160 180 0.000001a 0.0001a 0.001a 0.01a 0.1a 0.15a 0.3a 09652-075 figure 75 . ldo1, ldo2 ground current vs. input voltage, across output load (a), v out = 3.3 v ch2 ch3 a ch3 27.2m a 2 v out 30.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 20.0m 200s/div 5.0ms/s 200ns/pt i out 09652-076 figure 76 . ldo1, ldo2 response to load transient, i out from 1 ma to 80 ma, v out = 4.7 v ch2 ch3 a ch3 27.2m a 2 v out 30.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 20.0m 200s/div 5.0ms/s 200ns/pt i out 09652-077 figure 77 . ldo1, ldo2 response to load transient, i out from 10 ma to 200 ma, v out = 4.7 v ch2 ch3 a ch3 42.0m a 2 v out 30.0mv/div 50.0ma/div b w 20.0m 3 1m? b w 120m 200s/div 500ks/s 2.0s/pt i out 09652-078 figure 78 . ldo1, ldo2 response to load transient, i out from 1 ma to 80 ma, v out = 3.3 v ch2 ch3 a ch3 89.6m a 2 v out 50.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 120m 200s/div 500ks/s 2.0s/pt i out 09652-079 figure 79 . ldo1, ldo2 response to load transient, i out from 10 ma to 200 ma, v out = 3.3 v ch2 ch3 a ch3 89.6m a 2 v out 30.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 120m 200s/div 500ks/s 2.0s/pt i out 09652-080 figure 80 . ldo1, ldo2 response to load transient, i out from 1 ma to 80 ma, v out = 1.8 v
ADP5041 data sheet rev. 0 | page 22 of 40 ch2 ch3 a ch3 89.6m a 2 v out 50.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 120m 200s/div 500ks/s 2.0s/pt i out 09652-081 figure 81 . ldo1, ldo2 response to load transient, i out from 10 ma to 200 ma, v out = 1.8 v ch2 ch3 a ch3 27.2m a 2 v out 30.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 20.0m 200s/div 5.0ms/s 200ns/pt i out 09652-082 figure 82 . ldo1, ldo2 response to load transient, i out from 1 ma to 80 ma, v out = 1.2 v ch2 ch3 a ch3 27.2m a 2 v out 30.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 20.0m 200s/div 5.0ms/s 200ns/pt i out 09652-083 figure 83 . ldo1, ldo2 response to load transient, i out from 10 ma to 200 ma, v out = 1.2 v ch2 ch3 a ch3 4.84v 2 v out 20.0mv/div 1.0v/div b w 20.0m 3 1m? b w 20.0m 200s/div 1.0ms/s 1.0s/pt v in 09652-084 figure 84 . ldo1, ldo2 re sponse to line transient, input voltage from 4.5 v to 5.5 v, v out = 3.3 v ch2 ch3 a ch3 4.86v 2 v out 20.0mv/div 1.0v/div b w 20.0m 3 1m? b w 20.0m 500s/div 1.0ms/s 1.0s/pt v in 09652-085 figure 85 . ldo1, ldo2 response to line transient, input voltage from 4.5 v to 5.5 v, v out = 1.8 v ch2 ch3 a ch3 4.48v 2 v out 20.0mv/div 1.0v/div b w 20.0m 3 1m? b w 20.0m 200s/div 1.0ms/s 1.0s/pt v in 09652-086 figure 86 . ldo1, ldo2 re sponse to line transient, input voltage from 4.5 v to 5.5 v, v out = 1.2 v
data sheet ADP5041 rev. 0 | page 23 of 40 ch2 ch3 a ch3 4.02v 2 v out 20.0mv/div 1.0v/div b w 20.0m 3 1m? b w 20.0m 200s/div 1.0ms/s 1.0s/pt v in 09652-087 figure 87 . ldo1, ldo2 response to line transient, input voltage from 3.3 v to 3.8 v, v out = 1.8 v ch2 ch3 a ch3 4.84v 2 v out 20.0mv/div 1.0v/div b w 20.0m 3 1m? b w 20.0m 200s/div 1.0ms/s 1.0s/pt v in 09652-088 figure 88 . ldo1, ldo2 re sponse to line transient, input voltage from 3.3 v to 3.8 v, v out = 1.2 v 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3.6 4.1 4.6 5.1 5.6 output current (a) v in (v) v out = 3.3v 09652-089 figure 89 . ldo1, ldo2 output current capability vs. input voltage load (ma) rms noise ( v) 100 10 0.0001 0.001 0.01 0.1 1 10 100 1k 09652-104 ch2; v out = 3.3v; v in = 5v ch2; v out = 3.3v; v in = 3.6v ch2; v out = 2.8v; v in = 3.1v ch2; v out = 1.5v; v in = 5v ch2; v out = 1.5v; v in = 1.8v figure 90 . ldo1 output noise vs. load current, across in put and output voltage load (ma) rms noise ( v) 100 10 ch3; v out = 3.3 v ; v in = 5v ch3; v out = 3.3 v ; v in = 3.6v ch3; v out = 2.8 v ; v in = 3.1v ch3; v out = 1.5 v ; v in = 5v ch3; v out = 1.5 v ; v in = 1.8v 0.0001 0.001 0.01 0.1 1 10 100 1k 09652-105 figure 91 . ldo2 output noise vs. load current, across input and output voltage 10 100 1k 10k 100k 1m 10m frequenc y (hz) noise ( v/ hz) 100 10 1.0 0.1 0.01 09652-106 v out2 = 3.3 v , v in2 = 3.6 v , i load = 300m a v out2 = 1.5 v , v in2 = 1.8 v , i load = 300m a v out2 = 2.8 v , v in2 = 3.1 v , i load = 300m a figure 92 . ldo1 noise spectrum across output voltage, v in = v out + 0.3 v
ADP5041 data sheet rev. 0 | page 24 of 40 noise (v/hz) 100 10 1 0.1 0.01 1 10 100 1k frequenc y (hz) 10k 100k 1m 09652- 1 15 v out3 = 3.3 v , v in3 = 3.6 v , i load = 300m a v out3 = 1.5 v , v in3 = 1.8 v , i load = 300m a v out3 = 2.8 v , v in3 = 3.1 v , i load = 300m a figure 93 . ldo2 noise spectrum across output voltage, v in = v out + 0.3 v 100 10 1.0 0.1 0.01 10 100 1k 10k 100k 1m 10m frequenc y (hz) noise ( v/ hz ) 09652-108 v out2 = 3.3v, v in2 = 3.6v, i load = 300ma v out3 = 3.3v, v in3 = 3.6v, i load = 300ma v out2 = 1.5v, v in2 = 1.8v, i load = 300ma v out3 = 1.5 v , v in3 = 1.8 v , i load = 300m a v out2 = 2.8 v , v in2 = 3.1 v , i load = 300m a v out3 = 2.8 v , v in3 = 3.1 v , i load = 300m a figure 94 . ldo1 vs. ldo2 noise spectrum ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 300m a 09652-109 figure 95 . ldo2 psrr across output load, v in3 = 3.3 v, v out3 = 2.8 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 300m a 09652- 1 10 fi gure 96 . ldo2 psrr across output load, v in3 = 3.1 v, v out3 = 2.8 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 09652- 11 1 figure 97 . ldo2 psrr across output load, v in3 = 5.0 v, v out3 = 3.3 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 300m a 09652- 1 12 figure 98 . ldo2 psrr across output load, v in3 = 3.6 v, v out3 = 3.3 v
data sheet ADP5041 rev. 0 | page 25 of 40 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 300m a 09652- 1 13 figure 99 . ldo1 psrr across output load, v in2 = 5.0 v, v out2 = 1.5 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 300m a 09652- 1 14 figure 100 . ldo1 psrr across output load, v in2 = 1.8 v, v out2 = 1.5 v
ADP5041 data sheet rev. 0 | page 26 of 40 theory of operati on pw m/ psm c o n t r o l buck 1 dr i ver an d an t i sh oo t t hr o u g h r eset g en era t o r d eb o unc e vd d a vd d a psm c o mp l o w curr en t i l i m i t ad p 504 1 vo u t 1 fb1 vthr en w d vi n 1 a vi n sw pg n d en 1 enb k en l d o 1 en l d o 2 mo d e mo d e en 2 en 3 sel o pmo d e_ f u ses vi n 2 fb2 agnd vo u t 2 vi n 3 en l d o 1 60 0 ? enb k en l d o 2 60 0 ? mr vdda 52k? w d i vo u t 3 fb3 09652-090 oscillator thermal shutdown v ref watchdog detector nrsto vd da pwm comp gm error amp 85? soft start system undervoltage lock out enab l e and mo d e c o n t r ol ldo1 control ldo2 control figure 101 . functional block diagram power management uni t the ADP5041 is a micro power management unit (micro pmu) combing one step - down (buck) dc - to - dc regulator , two low drop out linear regulator s (ldo s ) , and a supervisory circuit , with watchdog, for processor control . the high switching frequency and tiny 20 - pin lfcsp package allow for a small power management solution. the regulators are act ivated by a logic level high applie d to the respective en pin . the en1 pin controls the b uck regulator, the en2 pin controls ldo1 , and the en3 pin controls ldo2. other features available on this device are the mode pin to control the b uck switching operation and a push - button reset input. t he r egulator output voltages and the reset threshold are set through external resistor dividers. when a regulator is turned on, the output voltage ramp is controlled th r ough a soft start circuit to avoid a large inrush current due to the discharged output capacitors. the buck regulator can operate in forced pwm mode if the mode pin is at a logic high level. in forced pwm mode, the switching frequency of the buck is always constant and does not change with the load current. if the mode pin is at a logic low level, the switching regulator operate s in auto pwm/psm mod e. in this mode, the regulator operate s at fixed pwm frequency w hen the load c urrent is above the power save current thresh old. when the load current falls below the power saving current threshol d, the regulator enters power saving mode , where the switching occurs in bursts. the burst repetition rate is a function of the current load and the output capacitor value. this operating mode reduces the switching and quiescent current losses.
data sheet ADP5041 rev. 0 | page 27 of 40 thermal pr otection in the event that the junction temperature rises above 150c, the thermal shutdown circuit turns off the b uck and the ldo s. extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temp e rature. a 20c hysteresis is included in the thermal shutdown circuit so that when thermal shutdown occurs, the buck and the ldo s do not return to normal operation until the on - chip temperature drops below 130c. when coming out of thermal shutdown, a ll r egulators start with soft start control . undervoltage lockout to protect against battery discharge, undervoltage lockout (uvlo) circu itry is integrated in the ADP5041 . if the input voltage on a vin drops below a typical 2.15 v uvlo threshold, all channels shut down. in the buck channel, both the power switch and the synchronous rectifier turn off. when the voltage on a vin rises above the uvlo threshold, the part is enabled once more. alternatively, the user can select device models with a uvlo set at a higher level, suitable for 5 v applications. for these models, the device reaches the turn - off threshold when the input supply drops to 3.65 v typical. enable/shutdown the ADP5041 ha s individual control pin s for each regulator. a logic level high applied to the enx pin activate s a regulator, whereas a logic level low turns off a regulator. active pull - down the ADP5041 can be ordered with the active pull - down option enabled. the pull - down resistors are conne cted between each regulator output and agnd. the pull - downs are enabled, w hen the regulators are turned off . the typical value of the pull - down resis tor is 600 for the ldos and 8 5 for the buck. buck section the buck use s a fixed frequency and high speed current mode architecture. the buck operate s with an input voltage of 2. 3 v to 5.5 v. the b uck output voltage is set th r ough externa l resistor divider s , shown in figure 102 . vout1 must be connected to the output capacitor. v fb1 is internally set to 0.5 v. the output voltage can be set from 0.8 v to 3.8 v. buck vout1 vout1 sw vin1 fb1 agnd 09652-091 c5 10f r1 r2 l1 ? 1h figure 102 . buck external output voltage setting control sch eme the buck operate s with a fixed frequency, current mode pwm control architecture at medium to high loads for high efficiency , but operation shifts to a power save mode (psm) control scheme at light loads to lower the regulation power losses. when operat ing in fixed frequency pwm mode, the duty cycl e of the integrated switches is adjusted and regulate s the output voltage. when operating in psm at light loads, the output voltage is controlled in a hysteretic manner , with higher output voltage ripple. dur in g part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. pwm mode in pwm mode, the buck operate s at a fixed frequency of 3 mh z , set by an internal oscillator. at the start of each oscillato r cycle, the pfet switch is turned on, sending a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the pfet switch and turns on the nfet synchro nous rectifier. this sends a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the rest of the cycle. the buck regulates the output voltage by adjusting the peak inductor current threshol d. power save mode (psm) the buck smoothly transition s to psm operation when the load current decreases below the psm current threshold. when the buck enter s power - save mode, an offset is introduced in the pwm regulation level, which makes the output volta ge rise. when the output voltage reaches a level that is approximately 1.5% above the pwm regulation level, pwm operation is turned off. at this point, both power switches are off, and the buck enters an idle mode. the output capacitor discharges until the output voltage falls to the pwm regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. this process is repeated while the load current is below the psm current threshold. the ADP5041 has a dedicated mode pin controlling the psm and pwm operation. a high logic level applied to the mode pin forces th e buck to operate in pwm mode. a l ogic level low sets the buck to operate in auto psm/pwm.
ADP5041 data sheet rev. 0 | page 28 of 40 psm current threshold the psm current threshold is set to 100 ma. the buck employs a scheme that enables this current to remain accurately con- trolled, independent of input and output voltage levels. this scheme also ensures that there is very little hysteresis between the psm current threshold for entry to, and exit from, the psm mode. the psm current threshold is optimized for excellent efficiency over all load currents. short-circuit protection the buck includes frequency foldback to prevent current runaway on a hard short at the output. when the voltage at the feedback pin falls below half the internal reference voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. the reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. soft start the buck has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. current limit the buck has protection circuitry to limit the amount of positive current flowing through the pfet switch and the amount of negative current flowing through the synchronous rectifier. the positive current limit on the power switch limits the amount of current that can flow from the input to the output. the negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% duty operation with a drop in input voltage, or with an increase in load current, the buck may reach a limit where, even with the pfet switch on 100% of the time, the output voltage drops below the desired output voltage. at this limit, the buck transitions to a mode where the pfet switch stays on 100% of the time. when the input conditions change again and the required duty cycle falls, the buck immediately restarts pwm regulation without allowing overshoot on the output voltage. ldo section the ADP5041 contains two ldos with low quiescent current that provide output currents up to 300 ma. the low 10 a typical quiescent current at no load makes the ldo ideal for battery-operated portable equipment. the ldos operate with an input voltage range of 1.7 v to 5.5 v. the wide operating range makes these ldos suitable for cascade configurations where the ldo supply voltage is provided from the buck regulator. each ldo output voltage is set though external resistor dividers, as shown in figure 103. v fb2 and v fb3 are internally set to 0.5 v. the output voltage can be set from 0.8 v to 5.2 v. ld01, ld02 09652-092 r a r b vin2, vin3 vout2, vout3 vout2, vout3 fb2, fb3 c7 2.2f figure 103. ldos external output voltage setting the ldos also provide high power supply rejection ratio (psrr), low output noise, and excellent line and load transient response with small ceramic 1 f input and 2.2 f output capacitors. ldo2 is optimized to supply analog circuits because it offers better noise performance compared to ldo1. ldo1 should be used in applications where noise performance is not critical. supervisory section the ADP5041 provides microprocessor supply voltage super- vision by controlling the reset input of the microprocessor. code execution errors are avoided during power-up, power- down, and brownout conditions by asserting a reset signal when the supply voltage is below a preset threshold and by allowing supply voltage stabilization with a fixed timeout reset pulse after the supply voltage rises above the threshold. in addition, problems with microprocessor code execution can be monitored and corrected with a watchdog timer. reset output the ADP5041 has an active low, open-drain reset output. this output structure requires an external pull-up resistor to connect the reset output to a voltage rail that is no higher than 6 v. the resistor should comply with the logic low and logic high voltage level requirements of the microprocessor while supplying input current and leakage paths on the nrsto pin. a 10 k resistor is adequate in most situations. the reset output is asserted when the monitored rail is below the reset threshold (v th ) or when wdi is not serviced within the watchdog timeout period (t wdi ). reset remains asserted for the duration of the reset active timeout period (t rp ) after the monitored rail rises above the reset threshold or after the watchdog timer times out. figure 104 illustrates the behavior of the reset output, nrsto, and it assumes that vout2 is selected as the rail to be monitored and supplies the external pull-up connected to the nrsto output.
data sheet ADP5041 rev. 0 | page 29 of 40 r st o n r st o vout2 vout2 vout2 0 v 1 v 0 v 1 v 0 v 09652-093 v th v th t rp t rp t rd t rd figure 104 . reset timing diagram the ADP5041 has a reset threshold programming input pin , vthr , to monitor a supply rail. the reset threshold voltage at vthr input is typically 0.5 v. to monitor a voltage greater than 0.5 v, connect a resistor divider network to the device as shown in figure 105 , where ? ? ? ? ? ? + = 2 2 1 5 . 0 r r r v v monitored 09652-094 v ref = 0.5v vthr monitored voltage r1 r2 figure 105 . external r eset t hreshold p rogramming do not allow the vthr input to float or to be grounded . c onnect it to a supply voltage greater than its specified threshold voltage. a small capacitor can be ad ded on vthr to improve the noise rejection and to prevent false reset generation. the ADP5041 can be factory programmed to a 2.25 v or 3.6 v uvlo thre shold. when monitoring the input supply voltage, if the se lected reset threshold is below the uvlo level , the reset output , nrsto , is asserted low as soon as the input voltage f alls below the uvlo threshold. below the uvlo threshold, t he reset output is m aint ained low down to ~1 v input voltage . t his is to ensure that the reset output is not released when there is sufficient voltage on the rail supplying a processor to restart the processor operations. manual reset input t he ADP5041 feat ure s a manual reset input ( mr ) which , when driven low, asse rts the reset output. when mr t ransitions from low to high, the reset remains asserted for the duration of the reset active timeout period before deasserting. the mr input h as a 52 k?, internal pull - up connected to avin, so that the input is always high when unconnected. an external push - button switch can be connected between mr and ground so that the user can generate a reset. debounce circuitry for this pu rpose is integrated on chip. noise immunity is provided on the mr input, and fast negative - going transients of up to 100 ns (typical) are ignored. a 0.1 f capacitor between mr and ground provides additional noise immuni ty. watchdog input the ADP5041 features a watchdog timer that mon itors microprocessor activity. the watchdog timer circuit is cleared with every low - to - high or high - to - low logic t ransition on the watchdog inpu t pin (wdi), which detects pulses as short as 8 0 ns. if the timer counts through the preset watchdog timeout period (t wd i ), an output reset is asserted. the microprocessor is required to toggle the wdi pin to avoid being reset. failure of the microprocess or to toggle wdi within the timeout period, therefore, indicates a code execution error, and the reset pulse generated restarts the microprocessor in a known state. as well as logic transitions on wdi, the watchdog timer is also cleared by a reset asserti on due t o an undervoltage condition on the monitored rail. when reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deasserts . the w atchdog timer can be disabled by leaving wdi floating or by three - stating the wdi driver. the ADP5041 can be factory programmed to two possible w atchdog time r values as indicated in table 18. wdi 1v 0v 0v 0v 09652-095 t rp t wd t rp v th v sensed nrsto figure 106 . watchdog timing diagram
ADP5041 data sheet rev. 0 | page 30 of 40 n o p o w e r po r st andb y r eset n o r ma l a vi n < vu vl o a ll en x = l o w a vi n > vu vl o end o f po r w d og 1 t i me o u t ( t wd ) en x = h ig h a c t i v e all regulators and supervisors activated a vi n < vu vl o a vi n < vu vl o end o f r eset pu l se (t r p ) 09652-096 i n t erna l c i rcu i t b i a sed r eg u l a t o r s an d su per vi so r y n o t ac t i va t ed no power applied to avin. all regulators and supervisory turned off transition state vmo n < vt h figure 107 . ADP5041 state flow
data sheet ADP5041 rev. 0 | page 31 of 40 a pplications information buck external compon ent selection trade - offs between performance parameters such as efficiency and transient response are made by va rying the choice of external components in the applications circuit, as shown in figure 1 . feedback resistors referring to figure 102, the total combined resistance for r1 and r2 is not to exceed 400 k . inductor the high switching frequency of the ADP5041 buck allows for the selection of small chip inductors. for best performance, use inductor values between 0.7 h and 3 .0 h. suggested ind uctors are shown in table 9 . the peak - to - peak inductor current ripple is calculated using the following equation: l f v v v v i sw in out in out ripple ? = ) ( where: f sw is the switching frequency. l is the inductor value. the minimum dc current rating of the inductor must be greater than the inductor peak current. the inductor peak current is calculated using the following equation: 2 ) ( ripple max load peak i i i + = table 9 . sugg ested 1.0 h inductors vendor model dimensions (mm) i sat (ma) dcr (m) murata lqm2mpn1r0ng0b 2.0 1.6 0.9 1400 85 murata lqm18fn1r0m00b 3.2 2.5 1.5 2300 54 tayo yuden cbc322st1r0mr 3.2 2.5 2.5 2000 71 coilcraft xfl4020 - 102me 4.0 4.0 2.1 5400 1 1 coilcraft xpl2010 - 102ml 1.9 2.0 1.0 1800 8 9 toko mdt2520 - cn 2.5 2.0 1.2 1350 85 inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (dcr). larger sized induct ors have smaller dcr, which may decrease inductor conduction losses. inductor core losse s are related to the magnetic permeability of the core mate rial. because the buck is a high switching frequency dc - to - dc conv erter , shielded ferrite core material is re commended for its low core losses and low emi. output capacitor higher output capacitor values reduce the output voltage ripple and improve load transien t response. when choosing the capacitor value, it is also important to account for the loss of capacita nce due to output voltage dc bias. ceramic capacitors are manufactured with a variety of dielec - trics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over t he necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are highly recom mended for best performance. y5v an d z5u dielectrics are not recommended for use with any dc - to - dc converter because of the ir poor temperature and dc bias characteristics. the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calcu - lated using the following equation: c eff = c out (1 ? tempco ) (1 ? tol ) where: c eff is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (t emp co) over ?40c to +85c is assumed to be 15% for an x5r dielec tric. the tolerance of the capacitor (tol) is assumed to be 10% , and c out is 9.24 f at 1.8 v, as shown in figure 108 . substituting these values in the equation yi elds c eff = 9.24 f (1 ? 0.15) (1 ? 0.1) = 7.0 7 f to guarantee the performance of the buck, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 0 2 4 6 8 1 0 1 2 0 1 2 3 4 5 6 dc b i a s vo lta g e (v) capacitance (f) 09652-097 figure 108 . typical capacitor performance the peak - to - peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: ( ) out sw in out sw ripple ripple c l f v c f i v = 2 2 8
ADP5041 data sheet rev. 0 | page 32 of 40 capacitors with lower equivalent series re sistance (esr) are preferred to guarantee low output voltage ripple, as shown in the following equation: ripple ripple cout i v esr the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 f and a maxim um of 40 f. table 10 . suggested 10 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j106 0603 6.3 taiyo yuden x5r jmk107bj106ma - t 0603 6.3 tdk x5r c1608jb0j106k 0603 6.3 panasonic x5r ecj1vb0j106 m 0603 6.3 the buck regulator require s 10 f output capacitors to guaran - t ee stability and response to rapid load variations and to transition in and out the pwm/psm modes. in certain applications wher e the buck regulator powers a processor, the operating state is known because it is controlled by software. in this condition, t he processor can drive the mode pin according to the ope rating state; consequently, it is possible to reduce the output capacitor from 10 f to 4.7 f because the regulator does not expect a large load var iation when working in psm mode ( see figure 109) . sw vi n 1 vi n 2 vi n 3 vo u t 1 vo u t 2 pg n d vo u t 3 l 1 1 h r 7 10 0k? c 1 10 f c 2 1 f c 3 1 f a vi n r fl t 30 ? v i n 2 . 3 v t o 5 . 5 v mi cr o pmu ad p 504 1 pr o c ess o r ana l o g sub sys t em vc o r e vdd i o r eset g pio 1 mo d e w d i g pio 2 en x g pio [x :y ] 3 09652-098 r5 fb3 r6 r1 r2 r3 r4 vanalog nr sto fb1 fb2 c6 2.2f c5 4.7f c7 2.2f figure 109 . processor system power management with psm/pwm control input capacitor a h igher value input capacitor help s to redu ce the input voltage ripple and improve transient response. maximum input capacitor current is calculated using the following equation: in out in out max load cin v v v v i i ) ( ) ( ? to minimize supply noise, place the input capacitor as close to the vin pin of the buck as possi ble. as with the output capacitor, a low esr capacitor is recommended. the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 f and a maximum of 10 f. a list of suggested capacitors is shown in table 11. table 11 . suggested 4.7 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j475me19d 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 panasonic x5r ecj - 0eb0j475m 0402 6.3 ldo e xternal c ompone n t s election feedback resistors t he maximu m value of rb is not to exceed 200 k (see figure 103). output capacitor the ADP5041 ldo s are designed for operation with small, space - saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with the esr value. the esr of the out put capacitor affects stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 ? or less is recom mended to ensure stability of the ldo . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the ldo to large changes in load current. when operating at output currents higher th an 200 ma a minimum of 2.2 f capacitance with an esr of 1 ? or less is recom mended to ensure stability of the ldo . table 12. suggested 2.2 f capacitors vendor type model case size voltage rating (v) murata x5r grm188b31a225k 0402 10.0 tdk x5r c1608jb0j225kt 0402 6.3 panaso nic x5r ecj1vb0j225k 0402 6.3 taiyo yuden x5r jmk107bj225kk - t 0402 6.3 input bypass capacitor connecting 1 f capacitor s from vin2 and vin3 to ground reduce s the cir cuit sensitivity to printed circuit board (pcb) layout, especially when long input t race s or high source impedance is encountered. if greater than 1 f of output capacitance is required, increase the input capacitor to match it.
data sheet ADP5041 rev. 0 | page 33 of 40 table 13. suggested 1.0 f capacitors vendor type model case size voltage rating (v) murata x5r grm1 55b30j105k 0402 6.3 tdk x5r c1005jb0j105kt 0402 6.3 panasonic x5r ecj0eb0j105k 0402 6.3 taiyo yuden x5r lmk105bj105mv - f 0402 10.0 input and output capacitor pro perties use any good quality ceramic capacitor with the ADP5041 as long as it meet s the minimum capacitance and maximum esr r equirements. ceramic capacitors are manufactured with a vari ety of dielectrics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary tempe - rature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best performance. y5v and z5u dielectrics are not recommended for use with any ldo because of their poor temperature and dc bias characteristics. figure 110 depicts the capacitance vs. dc voltage b ias chara cteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating . in general, a capacitor in a larger package or higher voltag e rating exhibits better stability. th e temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera - ture range and is not a function of package or voltage rating. 1 . 2 1 . 0 0 . 8 0 . 6 0 . 4 0 . 2 0 0 1 2 3 4 5 6 dc b i a s vo lta g e (v) capacitance (f) 09652-099 figure 110 . capacitance vs. voltage characteristic use the following equat ion to determine the worst - case capa - citance , accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) where: c bias is the effective capacitance at the operating voltage. tempco is the w orst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10% , and c bias is 0.94 f at 1.8 v , as shown in figure 110 . substituting these val ues into the following equation yields: c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0. 7 2 f therefore, the capacitor chosen in this e xample meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the pe rformance of the ADP5041 , it is imperative that the effects of dc bia s, temperature, and toler ances on the behavior of the capacitors be evaluated for each application. supervisory section threshold setting resistors referring to figure 105, the maximum value of r2 is not to exceed 200 k . watchdog input current to minimize watchdog input current (and minimize overall power consumption), leave wdi low for the majority of the watchdog timeout period. when driven high, wdi can draw as much as 25 a . pulsing wdi low - to - high - to - low at a lo w duty cycle reduces the effect of the large input current. when wdi is unconnected, a window comparator disconnects the watchdog timer from the reset output circuitry so that reset is not asserted when the watchdog timer times out. negative - going transien ts at the monitored rail to avoi d unnecessary resets caused by fast power supply transien ts, t he ADP5041 is equipped with glitch rejection circuitry. the typic al performance characteristic in figure 111 plots the monitored rail voltage, v th , t ransient duration vs. the transient magnitude. the curve show s combinations of transient magnitude and duration for which a reset is not generated . in this example, with the 3.00 v threshold, a transient that goes 100 mv below the threshold and lasts 8 s typically does not cause a reset, but if the transient is any larger in m agnitude or duration, a reset is generated. in this example , the reset threshold programming resistor values were r2 = 2 00 k , r1 = 1 m (see figure 105). 900 80 0 70 0 60 0 50 0 40 0 30 0 20 0 10 0 0 0 . 1 1 1 0 10 0 c o mpara t o r o verdr i ve (% o f v th ) transient duration (s) 09652-100 figure 111 . maximum v th transient duration vs. reset threshold overdrive
ADP5041 data sheet rev. 0 | page 34 of 40 watchdog software considerations in implementing the watchdog strobe code of the micro - processo r , quickly switching wdi low to high and then high to low (minimizing wdi high time) is desirable for current consumption reasons. however, a more effective way of using the watchdog function can be considered. a low - to - high - to - low wdi pulse within a given subroutine prevents the watchdog from timing out. however, if the sub - routine is held in an infinite loop, the watchdog cannot detect this because the subroutine continues to toggle wdi. a more effective coding scheme for detecting this error involves us ing a slightly longer watchdog timeout. in the program that calls the subroutine, wdi is set high. the subroutine sets wdi l ow when it is called. if the program executes without error, wdi is toggled high and low with every loop of the program. if the sub routine enters an infinite loop, wdi is kept low, the watchdog times out, and the microprocessor is reset (see figure 112). st ar t set w d i h ig h pr og ra m c o d e subr o u t i n e set w d i l o w r et ur n i n f i n i t e l oo p: w a t chd o g t i mes o u t r eset 09652-101 figure 112 . watchdog flow diagram power dissipation/thermal considerations the ADP5041 is a highly efficient micro power management unit (micro pmu ) , and in most cases the power dissipated in the device is not a concern. however, if the device operates at high ambient temperatures and wit h maximum loading conditions, the junction temperature can reach t he maximum allowable operating limit (125c). when the junction temperature exceeds 150c, the ADP5041 turns off all the regulators , allowing t he device to cool down. once the die temperature falls below 135c, the ADP5041 resumes normal operation. this section provides guidelines to calculate the power dissi - pated in the device and to make sure the ADP5041 operates below the maximum allowable junction temperature. the efficiency for each regulator on the ADP5041 is given by 100% = ( 1 ) where: is effi ciency . p in is the input power. p out is the output power. power loss is given by p loss = p in ? p out (2a) or p loss = p out (1 - )/ ( 2b ) the power dissipation of the supervisory function is small and negligible . power dissipation can be calculated in several ways. the most intuitive and practical is to measure the power dissipated at the input and all the outputs. the measurements should be performed at the worst - case conditions (voltages, currents, and temperature). the difference between input a nd output power is dissipated in the device and the inductor. use equation 4 to derive the power lost in the inductor, and from this use equation 3 to calculate the power dissipation in the ADP5041 buck regul ator. a second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, wheras the power lost on a ldo is calculated using equation 12. when the buck efficiency is known, use equation 2b to derive the total power lost in the buck regulator and inductor . u se equation 4 to derive the power lost in the inductor, and th en calculate the power dissipation in the buck converter using equation 3. add the power dissipated in the buck and in the ldos to find the total diss ipated power. note that the buck efficiency curves are typical values and may not be provided for all possible combinations of v in , v out , and i out . to account for these variations, it is necessary to include a safety margin when calculating the power dissi pated in the buck . a third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by equation 8 to equation 11 and the losses in the ldos provided by equation 12. buck regulator power dissipation the power loss of the buck regulator is approximated by p loss = p dbuck + p l ( 3 ) where: p d buck is the power dissipation on the ADP5041 buck regulator . p l is the inductor power losses. the inductor losses are exter nal to the device and they do not have any effect on the die temperature.
data sheet ADP5041 rev. 0 | page 35 of 40 the inductor losses are estimated (without core losses) by l rms out1 l dcr i p ? 2 ) ( ( 4 ) w here : dcr l is the inductor series resistance. i out 1(rms) is the rms load current of the buck regulator . /12 + 1 ) ( r i i out1 rms out1 = ( 5) where r is the normalized inductor ripple current . r v out1 (1 - d )/( i out1 l f sw ) (6) where: l is inductance . f sw is switching frequency . d is duty cycle. d = v out1 / v in1 (7) the ADP5041 buck regulator power dissipation, p d buck , includes the power switch conductive losses, the switch losses, and the transition losses of each channel. there are other sources of loss, but these are generally less significant at high output load currents, where the t hermal limit of the application is . equation 8 shows the calculation made to estimate the power dissipation in the buck regulator. p dbuck = p cond + p sw + p tran ( 8 ) the power switch conductive losses are due to the output c urrent, i out 1 , flowing through the pmosfet and the nmos f et power switches that have internal resistance, r dson - p and r dson - n . the amount of conductive power loss is found by : p cond = [ r dson - p d + r dson - n (1 ? d )] i out 1 2 (9 ) for the ADP5041 , at 125c junction temperature and vin 1 = 3.6 v, r dson - p is approximately 0.2 , and r dson - n is approximately 0.16 . at vin 1 = 2.3 v, these values change to 0.31 and 0.21 respectively, and at vin 1 = 5.5 v, t he values are 0.16 and 0.14 , respectively. switching losses are associated with the current drawn by the driver t o turn on and turn off the power devices at the switching frequency. the amount of switching power loss is given by : p sw = (c gate - p + c gate - n ) v in1 2 f sw ( 10) where: c gate - p is the pmosfet gate capacitance. c gate - n is the nmosfet gate capacitance. for the ADP5041 , the total of ( c gate - p + c gate - n ) is approximately 150 pf. the t ransition losses occur because the pmosfet cannot be turned on or off instantaneously , and the sw node takes some time to slew from near ground to near v out1 (and from v out1 to ground). the amount of transition loss is calculated by : p tran = v in1 i out1 (t rise + t fall ) f sw (11) where t rise and t fall are the rise time and the fall time of the switching node, sw. for the ADP5041 , the rise and fall time s of sw are in the order of 5 ns. if the preceding equ ations and parameter s are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. the converter performance also depends on the choice of pass ive compone nts and board layout; therefore, a sufficient safety margin should be included in the estimate. ldo regulator power dissipation the power loss of a ldo regulator is given by : p d ldo = [( v in ? v out ) i load ] + ( v in i gnd ) ( 12) where: i load is the load curre nt of the ldo regulator . v in and v out are input and output voltages of the ldo , respectively. i gnd is the ground current of the ldo regulator. power dissipation due to the ground current is small and it can be ignored. t he total power dissipation in the ADP5041 simplifies to : p d = {[ p dbuck + p dldo1 + p dldo2 ]} (13 ) junction temperature in cases where the board temperature , t a , is known, the thermal resistance parameter, ja , can be used to estimate the junctio n temperature rise. t j is calculated from t a and p d using the formula t j = t a + (p d ja ) (14 ) the typical ja value for the 20 - lead, 4 mm 4 mm lfcsp is 38 c/w (see table 7 ). a very important factor to consider is that ja is based on a 4 - layer , 4 in ch 3 in ch , 2.5 oz copper, as per jedec standard, and real applications may use different sizes and layers . to remove heat from the device, it is important to maximize the use of copper. copper exposed to air dissipates heat better than copper used in the inner layers. the exposed pad ( e p) should be connected to the ground plane with several vias as shown in figure 114. if the case temperature can be measured, the junction temperature is calculated by t j = t c + (p d jc ) (15 ) w here : t c is the case temperature. jc is the junction - to - case thermal resistance provided in table 7 . when designing an application for a particular ambient temperature range, calculate the expected ADP5041 power dissipation (p d ) due to the losses of all channels by u sing equation 8 to equation 13 . from this power calculation, the junction temperature, t j , can be estimated using equation 14.
ADP5041 data sheet rev. 0 | page 36 of 40 the reliable operati on of the buck regulator and the ldo regulator can be achieved only if the estimated die junction temperature of the ADP5041 (equation 14 ) is less than 125c. reliability and mean time between failures (mtbf) is highly affected by increasing the junction temperature. additional information about product reliability can be found in the analog devices, inc., reliability handbook , which is available at http:// www.analog.com/reliability_handbook . application diagram o n o f f f pw m pw m/ psm r filt 30? sw pg n d mo d e c4 10f l 1 1h vi n 1 en 3 en 1 vi n 2 vi n 3 en 2 a g n d vo u t 2 vo u t 1 fb3 vout3 vthr w d i n r st o c 1 4 . 7 f a vi n c 2 1 f c 3 1 f en _ b k buc k en _ l d o 1 l d o 1 (d igi t a l ) en _ l d o 2 l d o 2 (ana l og ) su per vi so r o n o f f o n o f f 4 2 0 1 6 1 3 1 0 7 6 3 ep 1 1 9 5 1 4 fb2 fb1 1 5 1 7 9 1 1 8 12 w d og r eset pu sh -bu tto n r eset mr main microcontroller 09652-103 r2 r1 2 r7 r8 c6 2.2f 1 8 vth r9 r4 r3 v out1 at 1.2a r6 r5 v dd c5 2.2f v in1 = 2 . 3 v t o 5 . 5 v v in2 = 1 . 7 v t o 5 . 5 v v in3 = 1 . 7 v t o 5 . 5 v v out2 at 300ma v out3 at 300ma figure 113 . application diagram
data sheet ADP5041 rev. 0 | page 37 of 40 pcb layout guideline s poor layout can affect ADP5041 performance, causing electro - magnetic in terference (emi) and electromag netic compatibility (emc) problems, ground bounce, and voltage losses. poor layout can also affect regulation and stability. a good layout is implemented u sing the following guidelines: ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high switching frequencies , and large tracks act as antennas. ? route the output voltage path away from the i nductor and sw node to minimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal dissipation. ? use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. suggested layout see figure 114 for an example layout. 0 . 5 1.0 1 . 5 2.0 2 . 5 3.0 3 . 5 4.0 4 . 5 5.0 1.0 2.0 3.0 mm mm g p l 5 . 5 6.0 6 . 5 avin vin 1 sw pgnd m r w d i v t h r m o d e agnd nrsto e n 2 4.0 5.0 6.0 g p l g p l g p l v o u t 3 v o u t 1 v o u t 2 p p l p p l 7.0 top layer p p l p i n 1 g p l g p l g p l g p l g p l g p l p p l p p l 09652-102 vias legend: ppl = power plane (+4v) gpl = ground plane 2nd layer 0.5 1.5 2.5 3.5 4.5 5.5 l1 ? 1h 0603 r filt 30? 0402 c1 ? 4.7f 10 v/xr5 0603 en 1 c2 ? 1f 10 v/xr5 0402 adp 5041 c5 ? 2.2f 6.3v/xr5 0402 c3 ? 1f 10v/xr5 0402 c6 ? 2.2f 6.3v/xr5 0402 vout 1 fb 1 vin 2 vout 2 fb 2 en3 vin 3 vout 3 fb 3 c4 ? 10 f 6.3v/xr 5 0603 figure 114 . suggested board l ayout
ADP5041 data sheet rev. 0 | page 38 of 40 bill of material s table 14. reference value part number vendor package c1 4.7 f, x5r, 6.3 v jmk107bj475 taiyo - yuden 0603 c2, c3 1 f, x5r, 6.3 v lmk105bj105mv -f taiyo - yuden 0402 c4 10 f, x5r, 6.3 v jmk107bj106ma - t taiyo - yuden 0603 c5,c6 2.2 f, x5r, 6.3 v jmk105bj225mv -f taiyo - yuden 0402 l1 1 h, 85 m ? , 1400 ma lqm2mpn1r0ng0b murata 2.0 1.6 0.9 (mm) 1 h, 85 m ? , 1350 ma mdt2520 - cn t oko 2.5 2.0 1.2 (mm) 1 h, 89 m ? , 1800 ma xpl2010 - 1102ml coilcraft 1.9 2.0 1.0 (mm) ic1 3-r egulator micro pmu ADP5041 analog devices 20- lead lfcsp
data shee t ADP5041 rev. 0 | page 39 of 40 factory programmable options table 15 . r egulator output discharge resistor options options description option 0 all discharge resistors d isabled option 1 all discharge resistors e n abled table 16. underv oltage lockout o ptions options min typ max unit option 0 1.95 2.15 2.275 v option 1 3.10 3.65 3.90 v table 17 . reset timeout options options min typ max unit option 0 24 30 36 m s o ption 1 160 200 240 m s table 18 . watchdog timer options selection min typ max unit option 0 81.6 102 122.4 m s option 1 1.28 1.6 1.92 s ec
ADP5041 data sheet rev. 0 | page 40 of 40 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd. 061609-b bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 2.65 2.50 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 115. 20-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-20-10) dimensions shown in millimeters ordering guide model 1 settings temperature range package description package option ADP5041 acpz-1-r7 wd t out = 1.6 sec t j = ?40c to +125c 20-lead lfcsp_wq cp-20-10 min reset t out = 160 ms v uvlo = 2.15 v discharge resistors enabled ADP5041 cp-1-evalz evaluation board 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09652-0-12/11(0)

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